GitHub

A bare metal programming guide

This guide is written for developers who wish to start programming microcontrollers using a GCC compiler and a datasheet, without using any framework. This guide explains the fundamentals, and helps ...
IEEE

Designing and Implementation of 32-bit 5 stage Pipelined MIPS based RISC Processor Capable of Resolving Data Hazards

Abstract: The main objective is to design and implement a 5-stage pipelined 32-bit High performance RISC Processor with MIPS architecture which is also capable in detecting and resolving Data Hazards.
GitHub

Mathematical Programming and Operations Research

The current release of this book can be found at here. This book was desigend originally for the undergraduete course ISE 3434 - "Deterministic Operations Research II" taught at Virginia Tech. I will ...
IEEE

Design and Implementation of Pipelined MIPS Processor with Nested Vectored Interrupt Controller (NVIC)

Abstract: MIPS (abbr. Microprocessor without Interlocked Pipelined Stages) based Pipelined Processor is a RISC (Reduced Instruction Set Computer) Processor [1][2]. The Processor is a 32-bit RISC ...
Microsoft

Wrex: A Unified Programming-by-Example Interaction for Synthesizing Readable Code for Data Scientists

Data wrangling is a difficult and time-consuming activity in computational notebooks, and existing wrangling tools do not fit the exploratory workflow for data scientists in these environments. We ...