GitHub

A minimal 8-bit processor using a Bit Serial Architecture

In a quest for a truly minimal computer, that can be built from readily available 74HC components on a low cost pcb, I have settled on a novel 8-bit, bit-serial architecture - a design that I call ...
IEEE

Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

Abstract: 32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triple-well 90 nm ...
GitHub

microsoft/vptq

Vector Post-Training Quantization (VPTQ) is a novel Post-Training Quantization method that leverages Vector Quantization to high accuracy on LLMs at an extremely low bit-width (<2-bit). VPTQ can ...
IEEE

2-Bit Wideband Electronically Controlled Reconfigurable Phased Array With Wide-Angle Beam-Scanning Capacity

Abstract: In this article, a 2-bit wideband electronically controlled reconfigurable phased array with wide-angle beam-scanning capacity is proposed. Based on the current reversal mechanism and ...