Semiconductor Engineering

Using SystemC TLM Modeling To Solve AI Data Movement Challenges

In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, ...
Design-Reuse

Transactional Level Modeling (TLM) of a High-performance OCP Multi-channel SDRAM Memory Controller

How the use of the OCP TLM SystemC library enhanced the design process of an OCP-based SDRAM controller IP, and dramatically improved the customer evaluation process. Introduction As a leading ...
EDN

Defining the TLM-to-RTL Design Flow

As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...
Design-Reuse

Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment

The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for ...
Electronic Design

SystemC Model Library Makes TLM Reuse Easier

Would-be users of transaction-level models (TLMs) and electronic system-level (ESL) design approaches in general face a major hurdle. Traditionally, it has been difficult to construct TLMs that serve ...
Semiconductor Engineering

Model Report Card

From its perspective as a leader implementing system level design methodology, STMicroelectronics is uniquely positioned to discuss issues and challenges related to the use of models in a variety of ...
Electronic Design

TLM-Based Verification Finds Strength In Standards

In design automation, as in other areas of the electronics industry, technologies and methodologies find broad acceptance through standardization. For example, the standardization of the Verilog ...