EDN

SoC Functional verification flow

This paper presents SoC- (System on Chip) level functional verification flow. It also describes ways to speed up the process. To ensure successful tapeout of SoCs, here are the steps of a standard SoC ...
Semiconductor Engineering

Verification As A Flow (Part 3)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Semiconductor Engineering

Gaps In The Verification Flow

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at Mentor Graphics; , CEO of Agnisys; , CEO of Test and ...
EDN

Accelerating Functional Verification

SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time ...
Business Wire

Aldec Launches ALINT-PRO-CDC Delivering Comprehensive CDC Verification Strategies for SoC and FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announces the release of ...
Electronic Design

The Verification Flow Can Enable Horizontal Reuse

Today's EDA companies now face the primary need for a verification flow that enables complete horizontal reuse of verification environments from concept to silicon and beyond. Big changes are ahead ...
Design-Reuse

COCONUT Project to Define a Modeling and Verification Flow for Embedded Platform Design

European research project named best proposal for embedded systems by the EU’s Seventh Framework Programme VERONA, Italy -- April 9, 2008-- In January 2008, work commenced on a European research ...
Embedded

Dealing with SoC hardware/software design complexity with scalable verification methods

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?
EurekAlert!

AI points toward a new paradigm for fully automated processor chip design

A Perspective in National Science Review outlines a new paradigm for fully automated processor chip design. By combining ...
Electronic Design

11 Myths About Verification IP

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...
Business Wire

OneSpin Solutions Announces 360 MV-Based Formal Verification Environment Adopted by Renesas Electronics Microcontroller Platforms

MUNICH & TOKYO & SUNNYVALE, Calif.--(BUSINESS WIRE)--OneSpin Solutions, an EDA company that provides innovative formal assertion-based verification solutions, today announced the adoption of its ...